Integrated circuit memory devices are widely used in many consumer and commercial applications. As the integration density of integrated circuit memory devices continues to increase, the number of memory cells in the integrated circuit memory devices may continue to increase. Moreover, the prefetch scheme for the integrated circuit memory devices also may continue to increase. As is well known to those having skill in the art, prefetch denotes how many simultaneous bits are written into or read from an integrated circuit memory array. The prefetch scheme may also be denoted by a burst length, i.e. how many bits are serially output or input to or from an external terminal in one operation. Many integrated circuit devices presently use a four-bit prefetch scheme, i.e., a four bit burst length. However, it may be desirable to increase to an 8-bit prefetch scheme or 8-bit burst length in order to operate a memory device at a higher data rate. In the future even higher prefetch schemes or burst lengths may be used.
Unfortunately, when increasing to a higher prefetch scheme, a write data path of the integrated circuit memory device may increase in size and/or complexity. As is well known to those having skill in the art, the write data path is used to serially receive multiple data bits from an external terminal and to provide the multiple bits to the memory cell array in parallel to write the multiple bits in the memory cell array. Thus, the write data path may take up an excessive amount of chip area.
FIG. 1 is a block diagram of a conventional Dynamic. Random Access Memory device (DRAM). DRAMs of FIG. 1 also may be referred to as a Fast Cycle DRAM (FCDRAM). As shown in FIG. 1, the FCDRAM 100 includes a clock buffer 102 that receives a clock signal and generates an internal clock signal, a command decoder 104 that generates commands from external inputs, an address buffer 106 that generates address signals from address data A0–A14 and bank selectors BA0, BA1, and a refresh counter 108. A control signal generator 110 generates control signals from the signals that are provided by the command decoder 104. A Mode Register Set (MRS) 112 generates mode signals as appropriate. An upper address latch 114 and a lower address latch 116 generate address signals that are applied to a row decoder and a column decoder, respectively. A burst counter 118 is used to control the burst length of read and write data. A write address latch/compare circuit 120 is used to compare previous and current write addresses.
Still continuing with the description of FIG. 1, four banks of memory cell arrays 122–128 may be provided. However, fewer or more banks may be provided. An input/output data path 200 includes a data control and latch circuit 130, a read data buffer 132 and a write data buffer 134 and an input/output (DQ) buffer 136. The DQ buffer 136 is responsive to a Data Mask (DM) signal that masks predetermined inputs. Operation of an FCDRAM as described in FIG. 1 is well known to those having skill in the art and need not be described further herein.
FIG. 2 is a more detailed block diagram of a data input/output path 200 of FIG. 1. As shown in FIG. 2, each of the data input/output terminals DQ0 . . . DQ15 serially receives 4 data bits that are transferred from the external terminal when the mode register 112 of FIG. 1 selects a burst length of 4. Then, each input data bit is transferred from a data input buffer 38 in the DQ buffer 136 to a serial-to-parallel (S-P) converter 30. The input data on the write data bus line (DBW) that is converted from serial-to-parallel by the serial-to-parallel converter 30, is transferred to an appropriate write data path 31, 32, 33, 34 that is selected by bank address bits BA0, BA1.
Still referring to FIG. 2, in order to read data, data is output from one of a plurality of banks Bank0–Bank3 and is transferred to the read data bus line (DBR) through a read data path 41, 42, 43, 44 that is selected by bank address bits BA0, BA1. The parallel data that is read on the DBR is then converted to serial data by a parallel-to-serial (P-S) converter 40. The serial data is then output externally through the data input and output terminals DQ0–DQ15 through the data output buffer 48. Accordingly, in some embodiments 64 bits (4 bits by 16) of input data can be written to a memory cell array of the selected memory bank at the same time and 64 bits of data can be read through the terminals DQ0–DQ15 at the same time.
FIG. 3 is a block diagram that illustrates a 4-bit prefetch scheme in a conventional FCDRAM, such as was described in connection with FIGS. 1 and 2. More specifically, referring to FIG. 3, when burst length 4 is selected by MRS 112 of FIG. 1, the first input data that is buffered from an input buffer 38 is stored in a first latch 311 of an input data latch 301 of the serial-to-parallel converter 30, in response to the rising edge of a first internal data strobe signal (PDS). The second bit of input data that is serially received is stored at a second latch 312 of the input data latch 301 of the serial-to-parallel converter 30 in response to the falling edge of the first internal data strobe signal (PDS).
At the same time, the first input data that is stored in the first latch 311 and the second input data that is stored in the second latch 312 are respectively transferred to a first register 313 and a second register 314 of a parallel converter 302 in response to a second internal data strobe signal PDSP. The third bit of input data is stored at the first latch 311 in response to the next rising edge of the first internal data strobe signal (PDS) and the fourth input data is stored in the second latch 312 in response to the next falling edge of the internal data strobe signal (PDS).
Also at the same time, the third input data bit and the fourth input data bit are respectively transferred to a third register 315 and a fourth register 316 of the parallel converter 302 in response to the rising and falling edges of the first internal data strobe signal (PDS). Thus, as shown in FIG. 3, odd input data DIN-0, such as the first and third input data bits, is consecutively transferred to the first and third registers 313 and 315 and even input data, such as the second and fourth input data bits, are transferred to the second and fourth registers 314, 316. After all input data D0, D1, D2, D3 is transferred to the parallel converter 302, all of the input data is then transferred and stored in parallel to a parallel data output circuit 303 in response to the rising edge of a third internal data strobe signal (PDSEN).
FIG. 4 is a timing diagram that illustrates the above operations including serial input of 4 data bits D0–D3 on the input DQ pad and the parallel output of the 4 data bits on output lines DBW_0–DBW_3.
Referring again to FIG. 3, the input data that is stored in the serial-to-parallel converter 30 is then stored in write data buffers 330, 331, 332 and 333 which form part of the write data path 31, 32, 33 or 34 of FIG. 2. From write data buffers 330–333, the input data is then transferred to the column select line (CSL) 350 in response to a control signal (PS4) that is applied to parallel bit switches PSW 340–343. The 4 bits of input data are written into the memory cell block 360 at the same time. Accordingly, FIGS. 3 and 4 illustrate a 4-bit prefetch scheme because 4 bits of data are written into a memory cell block at the same time. In FIG. 3, the lines that couple the write data buffers 330–333 to the parallel bit switches PSW 340–343 are referred to as Global Data Lines (GDL_0–GDL_3). The lines that couple the parallel bit switches (PSW) to the column select lines 350 are referred to as Local Data Lines (LDL_0–LDL_3). Finally, the bit lines of the memory cell array are denoted in FIG. 3 by BL_0–BL_511.
FIG. 5 is a block diagram of a conventional FCDRAM that includes an 8-bit prefetch scheme. As is well known to those having skill in the art, an 8-bit prefetch scheme may allow an FCDRAM to operate at a higher data rate. In FIG. 5, like numbers are used to designate like elements of FIG. 3. Moreover, in order to accommodate the 8-bit prefetch scheme, many of the elements of FIG. 3 are doubled in FIG. 5. Thus, a second set of registers 313′–316′ is provided in the parallel converter 302, as well as a second set of registers 317′–320′ in a parallel data output circuit 303. A second set of write data buffers 334–337 and a second set of parallel bit switches 344–347 also are provided.
As also shown in FIG. 5, the number of local data lines (LDL) and global data lines (GDL) are doubled compared to FIG. 3. Stated differently, in the 8-bit prefetch scheme of FIG. 5, the number of global data lines (GDL) and the number of local data lines (LDL) are increased two-fold compared to a 4-bit prefetch scheme of FIG. 3. More specifically, in FIG. 5, 8 global data lines (GDL_0–GDL_7) are used to connect a respective write data buffer 330–337 to a respective parallel bit switch 340–347. Moreover, 8 local data lines (LDL_0–LDL_7) are used to connect a respective parallel bit switch (PSW) 340–347 to the column select line 350. Unfortunately, the larger number of local and/or global data lines may increase the layout area of the integrated circuit memory device unduly.
Read and/or write data paths for other high-speed memory devices are illustrated in U.S. Pat. No. 6,144,616 to Suzuki et al. entitled “Semiconductor Memory Device”; U.S. Pat. No. 6,427,197 to Seigo et al. entitled “Semiconductor Memory Device Operating in Synchronization with a Clock Signal for High Speed Data Write and Data Read Operations”; and in published U.S. Patent Application 2001/0005012 to Ochuma et la. entitled “Fast Cycle Ram Having Improved Data Write Operation”.